Cadence Tools in the School of ECE Description of Mosis 0.5 micron technology library

Description of Mosis 0.5 micron technology library

Information is provided “as is” without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does and under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

The library layout is in absolute micron measurements, on a 0.15micron (half-lambda) grid. The DRC and EXT rules files can still be used with other submicron processes by changing a single line which defines the parameter “lambda”. We chose to use a half-lambda grid in order to use the MOSIS simple contact rules.

This library is for HP’s 0.5 micron process that can be used for version 4.4 of the Cadence suite of tools. The drc and extract rules (divaDRC.rul and divaEXT.rul) were written for diva and not dracula. In addition to the technology files, the library also contains all cells used in the HP 0.5 micron padframe. Included in the padframe are some additional pads (analog buffers, pullups, etc) that we commonly use in our designs. Also, in order to bring the MOSIS-supplied pad-protection circuitry into compliance with the MOSIS-supplied DRC rules concerning SilicideBlock and ESDxtors, we moved the edge of SiBlock so that it enclosed the xtor gate by exactly six lambda on both the left _and_ right sides (see x=158.55, y=193.25 in “zhp05__protection” layout).

We have also included “test” cells (DRCcheck and EXTcheck) that we used to confirm our technology files.

Please note, we designed the files so that the designer has to explicitly draw pwells around PMOS transistors (even though the entire substrate can be thought of a pwell). The reason we did this is to allow for separate grounds (e.g., digital and analog) in both the layout and schematic. Furthermore, the explicitly drawn pwells helps catch layout errors such as when ground signals of two separate sections are connected only through substrate. This is easily changed – there are comments within the DRC/EXT rules files indicating how to change back.

The technology files have been tested under cadence virtuoso and composer. As far as other tools, such as auto-place-and-route, the files are untested. Printer and plotter information is also untested at this moment.

Last revised March 30, 2007.